Microarchitectural Extension for Lifting-based DWT

At algorithmic level, the so called lifting scheme represents the fastest implementation of the Discrete Wavelet Transform (DWT). In this paper, we investigate a novel microarchitectural extension for the DWT based on the lifting scheme. A new fast lifting DWT (FLWT) instruction is introduced as an ISA Extension of a MIPS architecture. Simulations have been carried out by a cycle accurate simulator (SimpleScalar). As benchmark software, we have used a modified version of the package LIFTPACK, optimized for integer arithmetic. A microcodable DWT unit has been implemented on a reconfigurable hardware platform namely the Xilinx FPGA VIRTEX II. In order to accelerate the transform process, the hardware module utilizes pipelining, data reusability, data parallelism and some specific features of the Xilinx FPGAs. We have used the original synthesis tools of the FPGA vendor to get realistic data for the performance of the unit. Simulation results indicate a speedup of over 4 times versus the pure software implementation, assuming clock frequencies of 50 MHz for the DWT module and 1 GHz for the General Purpose MIPS. An important advantage of the module is that for higher degrees of the filter polynomial, its speed up versus the pure software implementation would be even higher. It is also noted that the speedup increases when the dimensions of the processed pictures grow. More dramatic improvements in performance can be achieved, since the design can be scaled-up to utilize higher degrees of parallelism. The introduced microarchitecture can be utilized by wavelet based encoding tools and standards like JPEG 2000, MPEG-4, etc. Keywords— Data compression, DWT, Lifting scheme, Microarchitecture, ISA Extension